数字逻辑电路的竞争与险象分析

Analysis on Race and Hazard of Digital Logic Circuits

对于数字逻辑电路,由于外界多个输入信号的同时改变,以及自身电路的传输延迟,因而普遍存在竞争现象。本文全面分析组合逻辑电路和时序逻辑电路中竞争出现的条件,对于会导致险象的临界竞争,针对不同的逻辑电路类型分别指出消除险象的具体措施。所得结论对数字逻辑电路分析和设计具有一定指导作用。

Race is a universal phenomenon existing in digital logic circuits due to the simultaneous change of two or more input signals and the transfer delay of logic circuits.The conditions in which race will occur are analyzed for combinational logic circuits and sequential logic circuits.Relative methods are presented to eliminate hazard resulted by critical race according to different types of logic circuits.The conclusion is useful for analysis and design of logic circuits.