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功耗-体系结构描述语言XP-ADL及其设计环境 被引量:2

Power-architecture Description Language XP-ADL and Design Environment
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摘要 降低计算机系统的功耗日益成为系统设计中的重要目标 ,可配置 VL IW体系结构在低功耗系统设计中具有显著的优势 .本文提出一种功耗 -体系结构描述语言 XP- ADL ,并介绍了基于该语言的体系结构设计环境 .XP- ADL语言将系统中各功能部件的结构表示和它们的执行 (功能 )语义分离开来 ,方便了可配置的 VL IW体系结构的描述 .同时 ,为了便于在功耗模型下进行体系结构空间探索 ,XP- Low power is becoming as a critical design target in current system design. Reconfigurable VLIW architecture has apparent advantages for low power design. This paper presents an architecture description language XP ADL for low power design and its architecture design environment. This language is firstly utilized in VLIW architecture design in our approach. XP ADL facilitates the description of reconfigurability by distinguishing construction information and execution information of system function units when describing reconfigurable VLIW architecture. The language and its environment also support various power models and power constraints by integrating basic power statistics in its grammar, which greatly facilitates the low power architecture design space exploration.
出处 《小型微型计算机系统》 CSCD 北大核心 2003年第8期1470-1473,共4页 Journal of Chinese Computer Systems
基金 国家自然科学基金项目 ( 60 2 73 0 42 )资助
关键词 功耗-体系结构描述语言 可配置VLIW 功耗模型 协同设计环境 power architecture description language reconfigurable VLIW power model codesign environment
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  • 1Bokar S. ISPD 2000 invited talk - EE times[M]. Apr. 14, 2000.73~73.
  • 2Luca Benini and Giovanni De Micheli. System-level power optimization: techniques and tools[J]. ACM Trans. On Design Automation of Electronic Systems, 2000,5(2):115~192.
  • 3Intel, Microsoft and Toshiba. Advanced configuration and power interface specification[S]. 1996.
  • 4Fisher J A. Very long instruction word architectures and the ELI-512[A]. Proc. 10^th Symp. Computer Arch[C]. ACM Press New York, 1983.
  • 5Brooks D, Tiwari V, and Martonosi M. Wattch:a framework for architectural-level power analysis and optimizations[C]. In:27th Annual International Symposium on Computer Architecture,June 2000.
  • 6Vijaykrishnan N, Kandemir M, Irwin M J, Kim H S and Ye W.Energy-driven integrated hardware-software optimizations using simplepower[C]. In: 27^th Annual International Symposium on Computer Architecture, June 2000.
  • 7Frenkil J. Issues and directions in low power design tools: an in dustrial perspective[A]. Proc. IEEE Int'l Syrup. Low Power Electronics and Design[C]. Aug. 1997, 152~157.
  • 8Gonzalez R and Horowitz M. Energy dissipation in general purpose microprocessors[C]. In:IEEE Intel. Syrup. On Low Power Electronics, Oct. 1995.
  • 9Sami M, Sciuto D, Silvano C, Zaccaria V. Instruction level power estimation for embedded VLIW cores[C]. In:Proc. CODES 2000.
  • 10Chen R, Irwin M, and Bajwa R. An architectural level power estimator[D]. Dept. CSE-Pennsylvania State Univ.,June 1998.

同被引文献14

  • 1Trimaran Comsortium.Timaran:an infrastructure for research in instruction-level parallelism.[2005-10-18].http://www.trimaran.org.
  • 2GYLLENHAAL J C,HWU W W,RAU B R.Hmdes version 2.0 specification[R].USA:Univ of Illinois,1996.
  • 3Schlansker M,Mahlke S,Johnson R.Control CPR:a branch height reduction optimization for EPIC architectures[C]//Proc ACM SIGPLAN 1999 Conference on Programming Language Design and Implementation.USA:ACM Press,1999:155-168.
  • 4LEUPERS R,Compiler design issues for embedded processors[J].IEEE Design & Test of Computers,2002,19 (4):51-58.
  • 5LEUPERS R,MARWEDEL P.Retargetable compiler technology for embedded systems-tools and applications[M].Netherlands:Kluwer Academic Publishers,2002.
  • 6B H Calhoun,C A P handrakasan.Standby power reduction using dynamic voltage scaling and canary flip-flop structures[J].Solid-State Circuits,IEEE Journal of Sept.2004,39(9).
  • 7R Mehra and J Rabaey.Exploiting regularity for low-power design[C].in Proc.ICCAD-96:IEEE/ACM Int.Conf.Computer Aided Design,San Jose,CA,Nov.1996.166-172.
  • 8Peter Petro and Alex Orailoglu.Low-Power Instruction Bus Encoding for Embedded Processors[J].IEEE Trans.VLSI Syst.,AUGUST 2004,12(8).
  • 9D Kim and K Choi.Power-conscious high-level synthesis using loop folding[C].in Proc.DAC-34:ACM/IEEE Design Automation Conf.,Anaheim,CA,June 1997.441-445.
  • 10Trimaran:An infrastructure for research in instruction-level parallelism.[R].ReaCT-ILP Laboratory,1999.

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