期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

软件流水的低功耗编译技术研究 被引量：5

Study on the Low Power Technology of Software Pipeline
下载PDF
导出
摘要 对具有可动态独立调整运行频率/电压的多功能部件配置结构M,基于全局调度的循环依赖关系,使用ILP形式化框架,研究了对给定循环L进行动态频率/电压调整的低功耗软件流水调度的编译优化技术,提出了一种合理而有效的低功耗最优化软件流水调度方法,使其在运行时保持性能不变而消耗的功耗/能量最小。 Based on loop-carried dependence of global schedule, the compiler optimization technology of low power software pipeline scheduling is studied as a kind of ILP formulation for a given loop ι under the configuration Μ with dynamic frequency/voltage scalable multi-function units. A reasonable and effective method of power-aware optimal software pipeline scheduling is proposed. It can make the loop run with minimized power/energy and without performance penalty.
作者 赵荣彩 唐志敏 张兆庆 Guang R.Gao
机构地区 信息工程大学计算机科学与技术系 中国科学院计算技术研究所 特拉华大学电子与计算机工程系
出处 《软件学报》 EI CSCD 北大核心 2003年第8期1357-1363,共7页 Journal of Software
基金 国家高技术研究发展计划(863)~~
关键词 软件流水 低功耗 编译优化 动态频率调整 并行处理 Calculations Computer software Formal logic Optimization Parallel processing systems Pipeline processing systems Scheduling
分类号 TP314 [自动化与计算机技术—计算机软件与理论]
  • 相关文献

参考文献1

二级参考文献8

  • 1Lo, J., Eggers, S., Levy, H., et al. Tuning compiler optimizations for simultaneous multithreading. In: Srimani, P., Fayad, M.E., eds. Proceedings of the 30th Annual International Symposium on Microarchitecture. Los Alamitos: IEEE Computer Society, 1997. 114～124.
  • 2Gao, G.R, Tang, Xinan, Wang, Jian, et al. Thread partitioning and scheduling based on cost model. In: Proceedings of the 9th Annual ACM Symposium on Parallel Algorithms and Architectures. New York: ACM Press, 1997. 272～281.
  • 3Theobald, K.B. EARTH: an efficient architecture for running threads [Ph.D.Thesis]. Montreal: McGill University, 1999.
  • 4Tullsen, D.M., Eggers, S.J., Levy, H.M. Simultaneous multithreading: maximizing on-chip parallelism. In: Sohi, Gurindar, ed. 25 Years of the InternationalSymposium on Computer Architecture: Selected Papers. New York: ACM Press, 1998.115～116.
  • 5Yang, Hong-bo, Gao, G.R., Marquez, A., et al. Impacts of loop optimizationon power consumption??a fresh look. In: Proceedings of the Workshop on Compilers and Operating Systems for Low Power (COLP) 2001. 2001. http://www.capsl.udel.edu/ ～hyang/personal.html.
  • 6Seng, J.S., Tullsen, D.M, Cai, G.Z.N. Power-Sensitive multithreaded architecture. In: Srimani, Pradip, ed. Proceedings of the International Conference on Computer Design 2000. Los Alamitos: IEEE Computer Society, 2000. 199～206.
  • 7Hsu, C-H., Kremer, U., Hsiao, M. Compiler-Directed dynamic voltage/frequency scheduling for energy reduction in microprocessors. In: International Symposium on Low Power Electronics and Design (ISLPED'01). 2001. 275～278. http://www.cs. rutgers.edu/～uli/pubs.html.
  • 8Seng, J.S., Tune, E.S., Tullsen, D.M. Reduceing power with dynamic critical path information. In: Williams, M., ed. Proceedings of the 34th Annual International Symposium on Microarchitecture. Los Alamitos: IEEE Computer Society, 2001. 114～123.

共引文献15

同被引文献33

引证文献5

二级引证文献7

软件学报
2003年 第8期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部