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基于序列对表示的对齐约束模块布局算法(英文) 被引量：2

A Block Placement Algorithm with Predefined Coordinate Alignment Constraint Based on Sequence Pair Representation
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摘要 在片上系统(SOC)的设计中,常常需要把某些单元摆放在某一预定坐标线附近相对较小的区域内,这一约束的来源是,在总线结构中,通过总线传递的数据,应当同步地出现在总线上,不能有较大的时延,对带有预定坐标线对齐(PCA)约束的模块布局问题进行研究,导出了约束模块之间的一系列关系,由此得到满足约束布局的必要条件。并且设计了多项式时间复杂度的算法,能够确保得到可行的模块布局。使用ami33和ami49对该算法进行了测试。实验结果证明,算法是有效的。 In the system on a chip, some cells should be placed along a predefined coordinate within a relatively small region. This constraint comes from the requirement that the data should be ready on the common bus at the same time. In this paper, the module placement problem is studied where some modules have the predefined coordinate alignment (PCA) constraint. The relations are given between constrained modules, from which a necessary condition is induced. A polynomial-time algorithm is developed that can guarantee a feasible placement is always obtainable. The algorithm is implemented and tested on ami33 and ami49. The experimental results show that it is effective.
作者 刘锐 洪先龙 董社勤 顾钧
机构地区 中国科学院软件研究所 清华大学计算机科学与技术系 香港科技大学计算机科学系
出处 《软件学报》 EI CSCD 北大核心 2003年第8期1418-1424,共7页 Journal of Software
基金 国家教育振兴计划(清华) 国家自然科学基金 国家重点基础研究发展规划(973)~~
关键词 模块布局 预定坐标线对齐约束 序列对 module placement predefined coordinate alignment constraint sequence pair
分类号 TP391 [自动化与计算机技术—计算机应用技术]
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参考文献13

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同被引文献23

  • 1Basaran A, Rutenbar RA. An O(n) algorithm for transistor stacking with performance constraints In: Proc. of the IEEE/ACM DAC.1996. 221-226.
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  • 4Bastos J, Steyaert M, Graindourze B, Sansen W. Influence of die bonding on MOS transistor matching. In: Proc. of the IEEE Int'l Conf. on Microelectronic Test Structures 1996. 17-31.
  • 5Murata H, Fujiyoshi K, Nakatake S, Kajitani Y. Rectangle-Packing-Based module placement In: Proc. of the IEEE Int'l Conf.Computer-Aided Design. 1995. 472-479.
  • 6Murata H, Fujiyoshi K, Nakatake S, Kajitani Y. VLSI module placement based on rectangle- packing by the sequence pair. IEEE Trans. Computer-Aided Design, 1996,15(11): 1518- 1524.
  • 7Nakatake S, Fujiyoshi K, Murata H, Kajitani Y. Bounded-Slicing structure for module placement Technical Report, Institute of Electronics, Information, and Communication Engineers (IEICE) 1994. 19-24.
  • 8Nakatake S, Fujiyoshi K, Murata H, Kajitani Y. Module placement on BSG-structure and IC layout applications In: Proc. of the IEEE Int'l Conf. Computer-Aided Design, 1996. 484-491.
  • 9Guo PN, Cheng CK, Yoshimura T. An O-tree representation of non-slicing floorplan and its applications In: Proc. of the 36th ACM/IEEE Design Automation Conf. 1999.268-273.
  • 10Hong XL, Huang G, et al. Comer block list: An effective and efficient topological representation of non-slicing floorplan. In: Proc.of the IEEE Int'l Conf. Computer-Aided Design 2000. 2000.

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软件学报
2003年 第8期

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