基于难测故障冲突分析的非扫描可测性设计

Non-scan testability based on fault-oriented conflict analysis

时序电路的测试生成非常复杂。时序电路的可测性设计对于指导电路设计及测试生成是十分重要的。基于对在测试生成过程中的难测故障进行冲突分析,提出了一种新的评价电路可测性的测度conflict+,并在此基础上提出了一种两阶段的非扫描可测性设计方法。这种新的测度可以体现出时序ATPG中的绝大部分特征。运用该方法对一些实验电路进行可测性设计后,结果表明比近期的两种非扫描可测性设计方法nscan和lcdft在故障覆盖率、测试效率等方面都取得了更好的效果。

Test generation for highly s equential circuits is quite complex so sequential circuits must be designed for testability to obtain good fault coverage and reduce test generation costs. A ne w testability measure based on the conflict analysis of hard-to-detect faults in the test generation process was used to develop a two-stage non-scan design for testability method. The new testability measure emulates most general featu res of sequential automatic test pattern generation (ATPG). The method was run o n a number of ISCAS benchmarks. The test results show that the proposed method p rovides better fault coverage and test efficiency than two recent non-scan desi gns for testability methods.