摘要
设计了一个双精度浮点乘法器。该器件采用改进的BOOTH算法产生部分积,用阵列和树的混合结构实现对部分积的相加,同时,还采用了快速的四舍五入算法,以提高乘法器的性能。把设计的乘法器分为4级流水线,用FPGA进行了仿真验证,结果正确;并对FPGA实现的时序结果进行了分析。
A doubleprecision floatingpoint multiplier is described in the paper For design of the device,modified BOOTH algorithm is used to generate partial products and a hybrid structure is used to reduce the length of critical path Also, a fast IEEE rounding scheme is adopted to improve the performance of the multiplier The multiplier is divided into 4stage pipeline,and it is synthesized and implemented on a Xilinx FPGA
出处
《微电子学》
CAS
CSCD
北大核心
2003年第4期331-334,共4页
Microelectronics