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一种双精度浮点乘法器的设计 被引量:2

A High Performance Double-Precision Floating-Point Multiplier
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摘要  设计了一个双精度浮点乘法器。该器件采用改进的BOOTH算法产生部分积,用阵列和树的混合结构实现对部分积的相加,同时,还采用了快速的四舍五入算法,以提高乘法器的性能。把设计的乘法器分为4级流水线,用FPGA进行了仿真验证,结果正确;并对FPGA实现的时序结果进行了分析。 A doubleprecision floatingpoint multiplier is described in the paper For design of the device,modified BOOTH algorithm is used to generate partial products and a hybrid structure is used to reduce the length of critical path Also, a fast IEEE rounding scheme is adopted to improve the performance of the multiplier The multiplier is divided into 4stage pipeline,and it is synthesized and implemented on a Xilinx FPGA
作者 何晶 韩月秋
出处 《微电子学》 CAS CSCD 北大核心 2003年第4期331-334,共4页 Microelectronics
关键词 浮点运算 BOOTH编码 IEEE舍入 浮点乘法器 阵列结构 Floating-point operation Multiplier BOOTH encoding IEEE rounding
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参考文献4

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  • 2Quach N, Takagi N, Flynn M J. On fast IEEE rounding [Z]. Technical Report CSL-TR-91-459,Stanford Univ. 1991.
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同被引文献10

  • 1徐晨,袁红林.基于VerilogHDL的IP核参数化设计[J].微电子学与计算机,2005,22(12):85-88. 被引量:3
  • 2刘鸿瑾,张铁军,侯朝焕.基于快速舍入的双精度浮点乘法器的设计[J].微电子学与计算机,2006,23(6):162-165. 被引量:2
  • 3胡正伟,仲顺安.10级流水线双精度浮点乘法器的设计[J].北京理工大学学报,2007,27(4):349-353. 被引量:1
  • 4[4]Alex Panato,Sandro Silva,Flávio Wagner,et al.Design of Very Deep Pipelined Multipliers for FPGAs[A].Proceedings of the Design,Automation and Test in Europe Conference and Exhibition Designers' Forum (DATE'04)[C].2004:52-57.
  • 5[5]ZHAO Junchao,CHEN Weiliang,WEI Shaojun.Parameterized IP Core Design[A].4th International Conference On ASIC PROCEEDINGS[C].Shanghai,China,2001.744-747.
  • 6Manolopoulos K, Reisis D, Chouliaras V A. An efficient multiple precision floating-point multiplier. Electronics[C]//Circuits and Systems (ICECS). Lebanon, Beirut, 2011.
  • 7Gong Renxi, Zhang Shangjun, Zhang Hainan. Hard-ware implementation of a high speed floating point multiplier based on FPGA[C]//Proceedings of 2009 4th International Conference on Computer Science Education. China: Wuhan, 2009.
  • 8Venishetti S K, Akoglu A. A highly parallel FPGA based IEEE-754 compliant double-precision binary floating-point multiplication algorithm[C]//Field-Programmable Technology. Taiwan: Taibei, 2007.
  • 9旷捷,毛雪莹,彭俊淇,黄启俊,常胜.基于FPGA的单精度浮点数乘法器设计[J].电子技术应用,2010,36(5):17-19. 被引量:3
  • 10孙海平,高明伦.8位RISC微处理器核的参数化设计[J].微电子学与计算机,2002,19(1):23-26. 被引量:4

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