一种高性能FFT处理器的VLSI结构设计

VLSI Architecture of a High Performance FFT Processor

针对高速数字信号处理的特点,研究了一种高性能FFT处理器的硬件结构。计算单元采用基4并行算法,使得基4碟形运算可以在一个时钟周期内完成,极大地提高了计算速度。根据该硬件结构,使用硬件描述语言和采用自顶向下的设计方法,完成了FFT处理器的电路设计。经硬件验证,达到设计要求。在系统时钟频率为100MHz时,1024点复数FFT的计算时间为12.8μs。

The VLSI architecture of a high performance FFT processor is described in the paper A particularly simple way to control radix4 FFT hardware is developed The method produces the indices both for inputs of each butterfly operation and for the appropriate twiddle factors The memory assignment is 'inplace' to minimize memory size,and memorybank conflictfree to allow simultaneous access to the four data needed for calculation of each of the radix4 butterflies,hence the processor can access all the operands concurrently in one cycle Using Verilog HDL,a 1024point FFT processor is designed,which can process frames of 16bit complex samples at one output sample per 100 MHz clock cycle,thus performing a 1024point transform in 128 μs