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以基本块为单位的非顺序指令预取 被引量：4

The Non-Sequential Instruction Prefetching Based on Basic Blocks
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摘要 取指令能力的高低对微处理器的性能有很大影响。指令预取技术能够有效地降低指令Cache的访问失效率,提高微处理器的取指令能力,进而提高微处理器的性能。本文提出了一种由分支指令指导的、以基本块为单位的非顺序指令预取技术,每次预取将一个完整的基本块读入指令Cache。这种方法使用静态策略分析程序行为,实现所需的硬件复杂度低。模拟结果显示,该方法能够有效地提高指令Cache访问的命中率。 Instruction supply can influence processor performance greatly.Instruction prefetching is an effective mechanism to reduce the instruction cache miss rate.This paper proposes a nonsequential instruction prefetching mechanism,which is directed by branch instructions and prefetches a whole basic block each time.Experimental results show it can increase the instruction cache hit rate effectively.In addition,it predicts program behaviors statically so that it does not need any complex hardware to predict and restore.
作者 沈立 戴葵 王志英
机构地区 国防科技大学计算机学院
出处 《计算机工程与科学》 CSCD 2003年第4期94-98,共5页 Computer Engineering & Science
基金 国家自然科学基金资助项目(60173040 6993303)
关键词 微处理器 指令处理模块 基本块 非顺序指令预取 执行模块 basic block instruction cache instruction prefetching branch prediction
分类号 TP332 [自动化与计算机技术—计算机系统结构]
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参考文献6

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同被引文献17

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引证文献4

二级引证文献7

计算机工程与科学
2003年 第4期

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