一种16×16位高速低功耗流水线乘法器的设计

A High-speed,Low-power,pipelined 16×16-bit multiplier design

提出了一种16×16位的高速低功耗流水线乘法器的设计。乘法器结构采用Booth编码和Wallace树,全加器单元是一种新型的准多米诺逻辑,其性能较普通CMOS逻辑全加器有很大改善。使用0.5μmCMOS工艺模型,HSPICE模拟结果表明,在频率为150MHz条件下,电源电压3.0V,其平均功耗为11.74mW,延迟为6.5ns。

A High-speed,Low-power pipelined16×16-bit mul-tiplier based on0.5μm CMOS Process is designed using Booth encoder,Wallace tree.A new'quasi-domino logic'structure has been adopted to increase the throughput rate for the full-adder cell.The simulatin shows that the multiplier can work up to150MHz with the average power11.74mW at a supply volt-age3.0V,and the latency is6.5ns.