一种高速浮点加法器的设计实现

An Approach of Design for High-Speed Floating-point Adder

浮点加法器是协处理器的核心运算部件,是实现浮点指令各种运算的基础,其设计优化是提高浮点运算速度和精度的关键途径。文章从浮点加法器算法和电路实现的角度给出设计方法,并且提出动态与静态结合设计进位链的方案以及前导0预测面积与速度的折衷方法。动态与静态结合设计进位链的方法有效地降低了功耗,提高了速度,改善了性能。目前已经嵌入协处理器的设计中,并且流片测试成功。

High-Speed Floating-point Adder is a critical part in the coprocessor,which is attached to the computing basis of floating-point instructions.The paper proposes a carry chain of dynamic and static mixed circuits and a good balance between speed and area of predicting leading-zero logic circuits,consid-ering algorithm and construction of logic circuits.The method improves the performance such as higher speed and lower pow-er.It has been embedded in the coprocessor,successfully pass-ing the product test.