ATM-PON系统中信元定界的并行处理

Parallel Disposal of Cell Delineation in ATM-PON System

基于异步传输模式 (ATM )的无源光网络 (PON -PassiveOpticalNetwork)系统传输汇聚层(TC)层的实现是通过VHDL语言 ,采用现场可编程门阵列 (FPGA)芯片来完成的 根据国际电信联盟 (ITU T)关于无源光接入网的G .983.1协议 ,ATM PON(APON)系统采用对称的 15 5M速率传输数据 ,为避免高速率下进行校验定界对ATM PON提出苛刻的要求 ,以及系统可能产生的不稳定性 ,在设计中采用了并行循环冗余校验 (CRC)算法 ,并且采用了并行的处理技术 本文具体介绍了TC层芯片设计过程中采用的几种并行处理技术 .

The TC sub-layer of APON system is implemented with FPGA chip by using VHDL language. According to the protocol of G.983.1, the data transfer speed of APON system is 155 Mb/s symmetrically. To avoid the strict requirement and the instability cased by the cell delineating in high data transfer speed, parallel CRC algorithm and parallel CRC method are used in the design. Several parallel disposal methods used in the design of TC sub-layer are introduced in this paper.