两相时钟方案

Two-phase clocking

选择时钟方案是同步时序集成电路设计的前提。本文阐述了两相时钟方案的规则,通过比较一相时钟与两相时钟方案,给出了两相时钟方案用于同步时序电路设计的优点。最后结合例子简要介绍了该方案在VERILOG HDL中的应用及其注意事项。

Selecting one clock scheme is the basis of designing synchronous systems . Two-phase clocking disciplines was given . Two-phase clocking was compared with one-phase clockingand its merits were given. Finally, how to use VERILOG HDL to describe two-phase clocking andsome caveat combined with example are introduced.