嵌入式Flash CISC/DSP微处理器的研究与实现

Study and Implementation of an Embedded Flash CISC/DSP Microprocessor

本文研究一种新的既具有微控制器功能 ,又有增强DSP功能的高性能微处理器的实现架构 .在统一的增强CISC指令集下 ,我们将基于哈佛和寄存器 寄存器结构的微处理器模块和单周期乘法 /累加器、桶形移位寄存器、无开销循环及跳转硬件支持模块、硬件地址产生器等DSP功能模块以及嵌入式FlashMemory和指令队列缓冲器有机的集成起来 ,在统一架构下通过单核实现CISC/DSP微处理器 ,有效地提高了处理器的性能 .该微处理器采用 0 35 μmCMOS工艺实现 ,芯片面积为 2 5mm2 .在 80M工作频率下 ,动态功耗为 4 2 5mW ,峰值数据处理能力可达 80MIPS .该处理器核可满足片上系统 (SOC)对高性能处理器的需求 .

A new architecture of an embedded Flash CISC/DSP microprocessor is presented. Under unified enhanced complex instruction set. The single core processor has been implemented by using RISC and pipeline design principles based on Harvard and register-to-register architecture. To achieve double functionality of DSP and general CPU, we have combined general CPU, embedded FLASH, instruction buffer and DSP functional units, such as single clock MAC, barrel shifter, fast loop processing unit, etc. in a single architecture. This processor is fabricated using 0.35 μm CMOS process, and the power consumption of the chip is less than 425 mW working under 3.3 V voltage and 80 MHz clock. The low-cost high performance microprocessor is well suited for a wide range of SOC applications.