摘要
通过对1个一位全加器3个输入端不同的组合,可以实现与门、或门、非门、同或门及异或门,因此全加器在数字逻辑电路中有着重要的作用.本文在介绍全加器的基础上提出了用查表法设计基于一位全加器实现任意三变量函数的组合电路和时序电路.在与传统的与非门/或非门的比较中,它显示了优势.
Because a one- bit full adder can realize AND,OR,NOT and some other gates, depending on the pattern of input connections, it plays an important role in the design of digital circuits. Based upon the discussion of full adders, a tabular design of three- variable combinational and sequential circuits by using one- bit full adders is proposed. Compared with conventional NAND and NOR gates, one- bit full adders have several advantages.
出处
《浙江大学学报（理学版）》
CAS
CSCD
2003年第5期518-523,共6页
Journal of Zhejiang University（Science Edition）
基金
浙江省科技厅资助项目(00111021).
关键词
数字逻辑电路
组合电路
时序电路
全加器
逻辑函数
查表法
full adder
logic synthesis
symmetric function
function classification
VLSI
LSI
trigger
