基于Spartan-6 FPGA的DDR2控制器接口设计

DDR2 SDRAM Memory Controller Interface Design Based on Spartan-6 FPGA

针对目前在高速、高精度、高存储深度的数据存储与通信系统中应用最为广泛的DDR2SDRAM存储器,利用ISE软件调用Xilinx的IP核产生Memory Controller Block(MCB),采用Verilog硬件描述语言实现对基于Xilinx公司FPGA架构的、基于工业标准的通用DDR2SDRAM控制器接口的设计与应用,分析了DDR2SDRAM的工作原理,重点研究了DDR2SDRAM的写操作、读操作、刷新操作,并且在Xilinx公司最新的Spar-tan-6系列的FPGA平台上验证了设计的正确性与稳定性。

The most widely used data storage memory is DDR2 SDRAM.It is currently used in high-speed,high-precision,and high-memory depth of the data storage and communication systems.The ISE software is used and the IP core of Xilinx is called to creat MCB.Besides the Verilog HDL is adopted to achieve a common DDR2 SDRAM controller interface for universal design and application based on the Xilinx’s FPGA chip and the industrial standard.The working principle of DDR2 SDRAM is analyzed,focusing on the read operation,write operation and refresh operation.Finally,the design accuracy and stability are validated in the latest Xilinx Spartan-6 series on the FPGA platform.