数字幅频均衡功率放大器

Digital Frequency - amplitude Capacity Balanced Amplifier

本作品以FPGA和单片机为核心控制器件,由前置放大模块、带阻网络模块、A/D采样模块、FPGA采样控制及存储模块、FPGA的FFT和IFFT计算模块、幅值均衡模块、D/A时钟控制模块等组成。系统的前置放大器电压增益达到56dB,带阻网络相对于10kHz时的输出幅值最大衰减可达-13.6dB,经过数字幅频处理之后,以10kHz时的输出幅值为基准,通频带20Hz～20kHz内的电压幅值波动在以内。系统在输入电压为5mVrms时,功率放大电路的输出功率可达12.75W,并且功率放大电路的效率可达71.6%,系统输出信号无明显失真。经过实际测试,系统各项指标达到了题目的设计要求。

This product with FPGA and SCM as core control unit consists of front-end amplifying modules,band reject network modules,A/D sampling modules,FPGA sampling control and storage modules,FPGA calculating modules FFT and IFFT,frequency balance modules,D/A clock control modules and so on.When voltage of the front end amplifier is up to 56dB,the out-put amplitude value of band reject under the frequency 10kHz reduces at most to-13.6dB.After handling of digital frequency amplitude,taking 10kHz out-put value as a benchmark, voltage fluctuation of transmission bands 20Hz～20kHz is within.When output voltage of the system is 5mVrms, output capacity will reach 12.75W,the circuit effect of capacity amplifier will get to71.6.and output signals will be without significant distortion.The system indexes meet design requirements after testing.