基于FPGA的TDC系统偏差修正方法的研究

TDC system deviation correction method research based on FPGA

随着TDC(time-to-digital converter)技术的广泛应用,对其精度的要求也越来越高。系统偏差作为TDC测量中不可避免的误差,通常由硬件结构、电路走线、测量过程等过程引入,其是否可以被有效修正直接影响着测量精度。为此,分析了基于FPGA(field-programmable gate array)的时间间隔测量的工作原理及系统组成,并搭建了硬件测试平台,进行了一系列时间间隔测量实验及系统偏差分析,结合FPGA测量原理,绘出了系统偏差修正方案并评估了时间间隔测量精度的影响。实验表明,建立有效的一次模型对测量结果进行拟合并对测量结果进行修正,可以将系统偏差控制在100ps以下,提高TDC测量准确度。

With the extensive application of time-to-digital converter(TDC)technology,the requirements for the accuracy of TDC are also increasing.The system deviation,as an inevitable deviation in TDC measurement,is mostly introduced by the hardware structure,circuit line,measurement process,etc.Whether it can be effectively modified directly affects the measurement accuracy.Therefore,in this paper,we analyze the working principle and system composition of time interval measurement based on fieldprogrammable gate array(FPGA).Meanwhile,a hardware test platform is built to conduct a series of timeinterval measurement experiments and system deviation analysis,and combined with FPGA measurement principle to draw up the system deviation correction program and evaluate the impact of the time-interval measurement.Experiments show that if an effective model can be established to fit the measurement results and correct the measurement results,it can hold the system deviation below 100 ps.As a result,the accuracy of TDC is significantly improved.