摘要
介绍了基于xilinx ISE 4.li设计平台的超大规模数字集成电路设计流程并使用Core- gen IP工具实现IP复用,在此基础上采用Virtex-Ⅱ器件完成了相参雷达高度表信号处理系统的单芯片实现(SOC)。以多普勒滤波器的设计为例子详细介绍Coregen IP的参数设计、数据格式转化及调用,并采用VHDL描述、原理图编辑(ECS)、CORE Generator等多种设计工具进行电路仿真和交互设计,最后给出部分仿真结果。
In the ISE 4.li design environment from Xilinx, based on the IP Resue technology using the tool of Coregen IP ,the signal processing system of Coherent Radar Altimeter is realized on a chip which belongs to the series device of Virtex-Ⅱ. The design of Doppler filter is taken as an example to illuminate how the parameters of the IP core are designed and how they are suited to design well. In the end, a part of simulation results of the project designed by VHDL Editor, Engineering Capture System(ECS), Core Generator are given.
出处
《信息与电子工程》
2003年第3期60-63,共4页
information and electronic engineering