摘要
超大规模集成电路技术的发展产生了一个复杂浩大的工程体系。已开展了通用CPU的LoadAligner数据通道部分的全定制设计 ,以此设计为例 ,阐述了一个集成电路子模块的逻辑设计、电路设计、版图设计 。
A complex IC engineering architecture is resulted in by advance in Very Large Scale Integration circuit (VLSI) technology. The design of Load Aligner in a general purpose CPU chip was carried out. In this paper, logic design, circuit design, layout and simulation about this project are talked of, and the relative results are also given.
出处
《电子工程师》
2003年第10期58-61,共4页
Electronic Engineer
基金
国家自然科学基金重大研究计划项目 (No .2 0 0 2AA1Z 0 3 0
No .90 2 0 70 2 1)
