FPU中一种高速乘法运算电路的设计与实现

A Design and Implement of a High-speed Multiplying Operational Circuit in FPU

在FPU的设计中,乘法运算电路是设计高精度高速度的乘法电路的重要部分,对提高整个FPU的性能具有重要的意义。通过对浮点处理单元(FPU)的体系结构的分析,比较了速度和规模分析并行通用乘法器之间的优缺点,结合FPU整体设计以及兼顾速度和规模,提出一种不同于通用乘法器设计的方法。该方法采用指数、尾数两条数据通道,用基-4的Booth算法和桶形移位寄存器,通过迭代完成乘法计算,并用VerilogHDL语言编写模块,用Modelsim进行仿真验证。这种方法速度快、占用硬件资源少,适于在FPU中实现,也可以做为一个独立的乘法器使用。

The multiplying operational circuit is an important part in the design of FPU. It is importance to design a highlyprecision and highlyspeeded multiplier in order to impove the unitary performance of FPU. In this paper, a structure of FPU is presented and a parallel special multiplier based both on the speed of the calculate and the scale of the design is analyzed, and their advantages and disadvantages are compared.Then,by considering both the whole design of FPU and the speed of the calculate and the scale of the design,the paper puts forward a design different from the special multiplier.The design adopts the double datapaths of both index and mantissa,and chooses the arithmetic of 4radix Booth and barreled shift register,and finally accomplishes multiplication with the overlapping arithmetic.The design programs in VerilogHDL and simulates and verifies in Modelsim.The design has some advantages as follows:higher calculating speed,less accounting for hardware resources and the application of accomplishment in FPU.Moreover,it could be used as a separate multiplier.