一种新的RLC互连解析延时模型的建立

A New Analytical Delay Model for RLC Interconnects

提出了用来评估深亚微米VLSI电路中RLC互连延时的一种新的解析延时模型.该模型的驱动器由输出电阻和电容组成,负载为容性负载.先对分布式均匀传输线的转换函数展开式进行二阶近似,然后根据不同的极点情况,计算出时域下的阶跃响应及相应的解析延时.该模型还被应用到具体的RLC互连树中评估源节点到漏节点的延时.实验结果表明,该模型比前人的延时模型精确,延时评估误差减少了10%;而由输出电阻和电容组成的驱动器能够很好地改善RLC互连树的延时分析.

This paper presented an innovative analytical delay model for RLC interconnects utilized in the estimation of interconnect delay for deep submicrometer VLSI circuits. The model has a driver, which comprises an output resistance and capacitance, and a capacitive load. Firstly, a second order approximation toward the expansion of transfer function for distributed uniform lines is conducted. Then the step response in time domain and the relevant analytical delay values are both calculated according to different poles. This delay model was also applied in the estimation of sourcesink delays in an interconnect tree. The preferable results were shown while compared with the previous delay models and the evaluation deviation is reduced by about 10%. Besides, it is also found that a driver consisting of a resistor and a capacitor can effectively improve the timing analysis of RLC interconnect trees.