一种SDRAM控制器软核的Verilog设计

A Verilog Design of SDRAM Controller Core

介绍了SDRAM存储器的特点及工作原理,SDRAM是一种采用了地址复用技术的高速海量同步存储器,其读写数据都是在时钟的上沿进行的。重点介绍了一种通用SDRAM控制器软核的Verilog设计,通过控制器接口可使得对SDRAM的操作如同通用的SRAM一样简单。

This paper introduces the characteristics and the work principle of the SDRAM.SDRA is a kind of RAM with high speed and vast capacity,which adress can be multiplicated.The read and write operation on the posedge of the clock.In emephases,this paper introduces the verilog design of a kind of all-purpose SDRAM controller core.By use the SDRAM controller interface,the SDRAM using are simple like the SRAM.