集群通信网络中的高速率位同步技术

On Making Highest Detection Working Frequency Equal to FPGA (Field Programmable Gate Array) Device′s Highest Working Frequency

采用 FPGA( Field Programmable Gate Array)器件实现高速集群通信中的多路数据同步检测时 ,由于受器件本身性能限制 ,难以设计出具有较高速率的数字锁相环 ( DPLL)电路。本文对采用 FPGA器件设计的高速率位同步电路 ,从通信可靠性角度进行了理论分析和实验 ,性能满足要求 ,而且电路检测最高工作频率可达器件的最高工作频率。

When using DPLL (digital phase locked loop) digital circuit in FPGA device, the highest detection working frequency is only a small fraction of FPGA device's highest working frequency. We propose designing a special capability into FPGA device to make the highest detection working frequency equal to FPGA′s highest working frequency. To implement our proposal, we need to study the super speed rate of synchronous technique for communication network of cluster. Section 1 discusses how to implement synchronous technique with a view to reaching our objective. Section 2 discusses how to replace DPLL digital circuit in FPGA device with another digital circuit that is convenient for reaching our objective. Section 3 gives our in depth theoretical analysis that explains why the new digital circuit proposed in section 2 is feasible. Section 5 discusses the environment under which we experimented: chip used was Altera's FPGA device APEX 20K 1(highest working frequency 264 Mb/s); transmission medium used was cat 5 UTP. The important experimental result was that, when the line transmission velocity was 125 Mb/s, the error rate for a line length of 10 m was of the order of magnitude of 10 -15 . It appears that the capability we designed into FPGA is a success.