基于CSD编码的高速乘法器IP设计

The Design of CSD Algorithm-based Fast Multipliers

符号数的正则表示(CSD)是一种用最少的非零比特位来表示符号数的编码技术。该文基于二进制补码数的CSD编码转换,结合采用优化技术,实现了对一组高速乘法器的IP核设计。采用Verilog硬件描述语言实现了设计的行为描述,在XilinxISE4.1环境下实现了功能仿真、综合和FPGA映射。其设计为小波变换核的开发提供了一个可重用的IP模块。

The Canonic Signal Digital(CSD)is based on the ternary number system(-1,0,1),which has the advantage of reducing the non-zero bits of the number.In this paper,a set of IP cores of high-speed multipliers,reusable for the development of wavelet transform core,based on CSD coding of2'complement ,are presented.The design is described by Verilog HDL,which is simulated,synthesized,and mapped into FPGA under Xilinx ISE4.1.