摘要
在高速数字系统设计中,信号完整性(SI)问题以及互连延迟引起的时序问题至关重要。详细分析推导了高速数字系统中各信号的信号完整性和传输延时约束关系,通过一个实例,给出了如何应用约束条件的具体方法。
In the high speed digital system design, signal integrity and propagation delay are pivotal. This paper analyzes and derives the signal integrity and constraints of propagation delays on various signals' trace in the high speed digital system in details. By means of a real example, the paper gives an individual method on how to apply the constraints.
出处
《计算机工程与设计》
CSCD
2003年第2期8-10,43,共4页
Computer Engineering and Design
基金
国家自然科学基金资助项目(69974005)
国家863高科技资助项目(2001AA114142)
