适于SoC的统一设计语言SystemVerilog

SystemVerilog—a unified design language for system-on-chip

顺应SoC的发展趋势,Accellera标准组织提议了一个统一设计语言SystemVerilog。本文主要讨论了SystemVerilog的特点、设计优势、现状和未来趋势等,并给出了一些实例。SystemVerilog是C、C++、Superlog和Verilog的混合,它极大地扩展了抽象结构层次的设计建模和验证的能力,是SoC设计的最佳统一语言。

With the trend of SoC design, a unified design language,SystemVerilog, isbeing proposed by Accellera. An overview of SystemVerilog is provided, including features,advantages, current status and future plan. Some examples are presented. SystemVerilog is a blendof C, C++, SUPERLOG and Verilog, which greatly extends the ability to model and verify designs atan abstract architectural level. It is a best unified design language for SoC.