多通道高速HDLC处理器的设计与实现

Design and Implementation of a Multi-Channel High Speed HDLC Data Processor

本文详述了由一个具有分时处理能力的HDLC处理器对 12 8逻辑通道数据进行高速、并行、实时处理的设计与实现过程 ,并讨论了其实现关键技术 ,给出了系统中关键结点的功能仿真波形图 .

This paper describes the design of a multi-channel high speed HDLC data processor which can process 128 logic channel HDLC data simultaneously. Its logic function and communication protocol coherence have been verified successfully by real-time operation system-vxWorks through FPGA. In the system, this multi-channel HDLC processor connects with 8 E1 physical links, and all 128 logic channel data separated from 256 timeslots of 8 E1 frames are processed by this single HDLC processor using time multiplex technology. Compared with other communication chips of this type, the above circuit structure takes more advantages in chip resources' taking up and channel management.