自偏置锁相环的相位噪声分析

Phase Noise Analysis of Self-Offset Phase Locked Loop

自偏置锁相环被提出以来,被认为能够以简单的电路结构降低锁相环的环内分频比从而改善环路带宽内的相位噪声。从噪声的相关性出发,分析了信号经过自偏置电路后对相位噪声的影响,并通过计算自偏置锁相环的相位传递函数得到其相位噪声模型,对比于传统单环式锁相环结构,其环内分频比并未降低。通过设计一2.28~2.52GHz的自偏置锁相环,对其相位噪声进行测试并与传统单环和偏置式锁相环进行比较,测试结果也表明自偏置锁相技术并不能降低锁相环的带内相位噪声。

The proposed self-offset phase locked loop( PLL) with simplified circuit structure has been considered to improve the phase noise performance in loop bandwidth by decreasing the frequency divide-ratio in the loop. Based on the correlation property of the noise,the effect of the self-offset circuit has been analyzed on phase noise performance in this article,and the phase noise model has been obtained by calculating the phase transfer function. It can be shown that the frequency divide-ratio of the loop has not been reduced compared to conventional single-loop PLL. In order to verify the theory analysis,a 2. 28 ~ 2. 52 GHz self-offset PLL circuit has been designed and implemented. The measurement results also indicate that the self-offset phase locked technology cannot improve the phase noise performance in loop bandwidth compared to conventional single-loop and offset PLLs.