110GHz阻性平衡三倍频器设计

Design of a 110GHz Balance Resistive Tripler

本文介绍了一种基于阻性肖特基二极管芯片UMS DBES105a的110GHz三倍频器,通过两个芯片反向并联形成了平衡结构,同时提高了倍频器的功率承受能力。电路设计中使用二极管三维电磁模型,匹配设计时未设计专门的输入过渡和滤波器,而是直接经行匹配设计,提供了更多的可优化参量,以达到最佳的匹配效果和带宽。经过HFSS和ADS联合仿真,在频率为31~44GHz,功率为20d Bm的驱动信号激励下,三倍频器输出频率大于7d Bm,最大输出功率为9.1d Bm@105GHz。

This paper reports a 110 GHz tripler based on resistive Schottky diode chip, two chips are placed antiparallel to form a balanced structure, and also this improves the power handling capability same time. A 3D diode electromagnetic model is used during circuit design, input probe transition and filter are not designed specifically to match the diodes, but a novel direct matching method is adopted which could provide more parameters to optimize that can achieve the best matching results and bandwidth. After co-simulation with HFSS and ADS, when driven by 20 d Bm power from 31 GHz to 44 GHz, the tripler can output a power great than 7d Bm, maximum output power is 9.1d Bm at 105 GHz.