基于Cadence的接收机信号完整性设计

Design for Signal Integrity of Receiver Based on Cadence

高速数字电路中的信号完整性问题本质上是一个复杂的电磁场问题,人工计算难以对其进行定量分析。Cadence相比于其它EDA工具,可针对高速数字电路设计的不同阶段进行仿真,并根据仿真结果对PCB设计进行条件约束。本文依据仿真结果,通过调整层叠结构、优化匹配电阻、约束线间距及耦合长度等措施,提高PCB信号质量。电路PCB布线完成后,对关键信号进行仿真,验证布局、布线的可靠性。

The nature of signal integrity problems on high-speed digital circuits is a complex electromagnetic problems, therefore, signal integrity problems are difficult to be quantitatively analyzed by manual calculation. Compared to other EDA tools, Cadence can simulate for different stages of the high-speed digital circuit design, and set constraint condition for PCB design based on the simulation results. This paper based on the simulation results, adjusting the characteristic impedance of each signal layer structure traces, optimizing matching resistance, restricting line spacing and coupling length, to improve signal quality. After completion of the circuit PCB layout, validate the reliability of wiring and layout by simulating the critical signals.