一种基于FPGA的RS编译码器设计与实现

Design and implementation of a RS encoder and decoder based on FPGA

RS码是线性分组码中具有很强纠错能力的多进制BCH码,其在纠正随机错误和突发错误方面非常有效,因此被广泛应用于通信和数据存储系统。本文提出了一种实现复杂度低、高效率的RS编译码器实现电路,包含RS编码器、Horner准则的伴随式计算、BM算法、Chien搜索等模块,以RS(15,9)为例运用VHDL在ISE14.6软件环境下进行了功能仿真,结果与Matlab得到的理论结果一致。该方法适用于任意长度的RS编码,有着重要的应用价值。

RS code is a linear block code with a strong error correction ability of the multi band BCH code, which is very effective in correcting random errors and burst errors,so it is widely used in communication and data storage systems. In this paper, the results are consistent with a theory to achieve low complexity and high efficiency of the RS compiled code realization circuit,with computing,BM algorithm,Chien search module that contains a RS encoder, Horner criteria,to RS(15,9) as an example using VHDL in ISE14.6 software under the environment of the function simulation,the results with MATLAB software.This method can be applied to any length RS code, and it has important application value.