摘要
本文设计和研究了一种低功耗12Bit流水线模数转换器的结构,其采用了TSMC 0.18um工艺设计,3.3V单电源电压,5MHz采样率,动态范围为1V,INL为0.5LSB,DNL为2LSB,通过详细的电路原理分析和软件Cadence的仿真,并流片测试,性能达到设计初衷。
This paper study and design a kind of low power consumption structure of 12 bit pipeline adc, the adopted TSMC 0.18 um process design, single power supply voltage of 3.3 V,5 MHZ sampling rate and dynamic range of 1 V, INL 0.5 LSB, DNL is 2 LSB, through detailed analysis of the circuit principle and software simulation, Cadence and flow testing, performance meet the design intent.
出处
《电子测试》
2016年第9X期23-24,共2页
Electronic Test
