0.18μm CMOS Σ-Δ ADC用数字抽取滤波器设计

Design of a Digital Decimation Filter for Σ-Δ ADC in 0.18 CMOS

采用标准0.18μm CMOS工艺,设计了一种应用于UHF RFIDΣ-Δ模数转换器的数字抽取滤波器,并完成其前后仿真、逻辑综合、布局布线及版图实现等全流程.该滤波器主要实现滤波和降采样功能,由梳状滤波器、补偿滤波器和半带滤波器级联组成.合理选择各级滤波器的结构、阶数并采用规范符号编码(CSD)对其系数进行优化.仿真结果表明:采样频率为64MHz,过采样率为32的二阶Σ-Δ调制器的输出1位码流经过该滤波器滤波后,信噪比达到53.8dB;在1.8V工作电压下,功耗约为15mW.版图尺寸0.45mm×0.45mm,能够满足RFID中模数转换器的要求.

Design of a digital decimation filter for UHF RFIDΣ-ΔADC in 0.18μm CMOS process,and complete the entire process,including pre and post-simulation,logic synthesis,floorplan,and layout design,etc.The filter use comb filter,compensation filter and half-band filter cascade to achieve filtering and down-sampling.Rational choice of archi-tecture and order and the optimal of coefficient with CSD coding.With sampling frequency of 64MHz,and oversampling ratio of 32,simulation results showed that by processing the bit stream from a 2-orderΣ-Δmodulator, a signal-to-noise distortion ratio(SNDR)of 53.8dB is obtained for the filter.In the operating voltage of 1.8V, the power consumption is 15mW,layout area 0.45mm×0.45mm,and can meet the demand of RFIDΣ-ΔADC.