低相位噪声压控振荡器的设计及仿真

A LC Voltage-Controlled Oscillator Design and Simulation

随着通信技术对射频收发机性能要求的提高,高性能压控振荡器已成为模拟集成电路设计、生产和实现的关键环节.针对压控振荡器设计过程中存在相位噪声这一核心问题,采用STMC 0.18μm CMOS工艺,提出了一种1.115GHz的电感电容压控振荡器电路,利用Cadence中的SpectreRF对电路进行仿真.仿真结果表明:在4~6V的电压调节范围内,压控振荡器的输出频率范围为1.114 69~1.115 38GHz,振荡频率为1.115GHz时,在偏离中心频率10kHz处、100kHz处以及1MHz处的相位噪声分别为-90.9dBc/Hz,-118.6dBc/Hz,-141.3dBc/Hz,以较窄的频率调节范围换取较好的相位噪声抑制,从而提高了压控振荡器的噪声性能.

With the rapid improvement on the communication technology of RF transceiver , high performance voltage-controlled oscillator has been the key link of analog integrated circuit design , production and implementation .Focus on the problem of phase noise ,a design for a 1 .115 GHz LC VCO is proposed in TSMC 0.18 μm CMOS process .The circuit is simulated by the SpectreRF in Cadence .The simulation results presented that the VCO voltage adjustment range is 4 V to 6 V ,and output frequency range is 1 .114 69 GHz to 1 .115 38 GHz .Phase noise at an offset of 10 kHz ,100 kHz and 1M Hz are -90 .9 dBc/Hz ,-118 .6 dBc/Hz and -141 .3 dBc/Hz ,respectively .In order to enhance the VCO noise performance ,the paper’s purpose is as much as possible to exchange narrow frequency for good phase noise .