一种QC_LDPC码译码器的设计

Design of High-Performance QC_LDPC Decoder

根据BP译码算法,设计了一种高速部分并行QC_LDPC码译码器结构,该结构适用于所有其校验矩阵具有准循环特性的LDPC码.针对传统BP译码器的结构复杂度高,系统运行频率低和吞吐率小等特点,本设计将BP译码算法中大量的复杂函数运算通过查找表的方法来实现;校验节点和变量节点的处理均采用5级流水线的方式;采用提前终止迭代译码策略.本设计能有效地减少译码器硬件实现复杂度,同时提高系统运行地频率和数据吞吐率.

Based on the belief propagation(BP)decoding algorithm,a high-speed partially parallel decoder architecture suited for quasi-cyclic low density parity check(QC_LDPC)codes is designed.It is applicable to all the QC_LDPC codes.In view of the traditional BP decoders have complex architecture,low system operating frequency and low throughput features,three improved methods are proposed.Firstly large number of complex function operations can be achieved through a look up table.Secondly,check nodes and variable nodes are all use 5-stage pipeline for processing.Last early termination strategy is adopted.This design can effectively reduce the complexity of the hardware implementation of the decoder,at the same time improve the frequency and the decode throughput of the system.