SM3杂凑算法的ASIC设计和实现

Design and Implementation of SM3 Algorithm in ASIC

针对国家商用密码SM3杂凑算法提出了一种四合一的ASIC实现架构.该架构采用进位保留加法器和循环展开方式,与单轮结构相比,时钟周期数减少了75%,吞吐率提高了29.4%.采用65nm的SMIC工艺,在125MHz的低时钟频率下,吞吐率达到了4Gb/s.此款SM3杂凑算法芯片已经进行了流片,支持填充和暂停功能.

Based on the analysis of the National Business password the SM3 hash algorithm,a four-to-one architecture is proposed.The architecture uses carry-save adder and loop unrolling to improve its performance.Compared with single cycle architecture,the four-to-one architecture reduces the number of clock cycles by 75% and improves the throughput by 29.4%.In SMIC's 65 nm process,the throughput of SM3 has achieved a high performance of 4Gbps at 125 MHz.This SM3 hash algorithm chip is being taped.It supports byte padding and has pause function.