一种高精度Σ-Δ数模转换器的设计

Design of a High Precision Σ-ΔD/A Converter

为满足无线通信应用中对数据精度的要求,设计了一款高精度的Σ-Δ数模转换器(Σ-ΔDAC).用半带滤波器、梳状滤波器和采样保持电路实现64倍的过采样,其中的半带滤波器采用了一种改进的结构,有效地减小了整个插值滤波器所占的面积.Σ-Δ调制器采用单比特量化单环结构,降低系统对后级模拟部分非理想特性的敏感度.对于带宽400kHz、采样频率1MHz的输入数字信号,整个系统的信噪比为113dB,有效位数达18bit.

This paper designs a high-precision Sigma-Delta Digital-to-Analog Conver(Σ-Δ DAC) ,to meet the data accuracy in wireless communication applications . The 64-time-oversampling interpolator consists of a half-band filter ,a CIC filter and a sample-hold circuit ,in w hich the half-band filter uses an improved implementation and saves the area consumption effectively .The Σ-Δ modulator uses single-bit quantized single-loop 5th-order structure to reduce the sensitivity of the non-ideal characteristics of the analog parts .For the digital input signal with 400 kHz bandwidth and 1 M Hz sample rate ,the simulated SNR is 113 dB and the Effective Number of Bits (ENOB) is 18 bits .