应用EDA技术实现并列乘法器

Realization of Parataxis Multiplicative Implement by Application of EDA

阐述了EDA技术的基本特征和作用,详细介绍了EDA技术在实现数字系统——并列乘法器中的应用。采用层次化设计,使用Altera公司的MAX+PLUSⅡ10.0的开发软件。整个系统被划分为4个子模块,使用VHDL语言或图形描述,经编译、优化、仿真,成功地完成了并列乘法器的功能模拟,并下载现场可编程逻辑阵列(FPGA)FLEX10K逻辑器件,从而实现了整个设计。通过这一实例可以看出,EDA技术在现代数字系统设计中的作用,它替代了传统的逻辑功能固定的集成块加连线的设计方法,已经成为电子系统设计的新潮流。

The basic characteristics and function of EDA (Electronics Design Automation) technology were reported. The application of EDA in realizing digital system - parataxis multiplication implement was particularly introduced. It showed that the whole design took the administrative levels. By using MAX + PLUS II 10.0 developed by Altera company, the whole system eould be divided into four submodules described by VHDL and schematic diagram. It succeeded in function simulation and implement of parataxis multiplication implement, thus all the design was completed. Through the example, we can see EDA technology has an important role in modern digital system design, which has become a new tideway in electronic system design.