设计可综合状态机几种状态编码方式的比较

The Comparison of State Encoding Style for Designing Synthesizable State Machine

本文介绍了采用verilog硬件描述语言设计有限状态机时几种常用的状态编码方式,并结合有限状态机的设计例子来比较各编码方式。

This paper discusses several state encoding styles in designing finite state machine using verilog HDL, and then compares these styles by an example.