摘要
介绍一种由AD9851和LMX2306构成的DDS+PLL结构的锁相环路,具有参数设置灵活、频率稳定度高的优点,根据实验结果对环路指标进行了分析计算。该方案已在实际工程中采用。
A DDS+PLL implementation for clock synchronism is presented, being excellent in parameters setting and frequency stability. Some parameters of the PLLs are analyzed and studied according to the experimental data. This scheme has been used in practical engineering.
出处
《电讯技术》
北大核心
2003年第6期51-54,共4页
Telecommunication Engineering
基金
广东省自然科学基金资助项目(000840)
