期刊文献+

新结构MOSFET 被引量:1

An Overview of MOSFET's with Novel Structures
下载PDF
导出
摘要  和传统平面结构MOSFET相比,新结构MOSFET具有更好的性能(如改善的沟道效应(SCE),理想的漏诱生势垒降低效应(DIBL)和亚阈值特性)和更大的驱动电流等。文章主要介绍了五种典型的新结构MOSFET,包括平面双栅MOSFET、FinFET、三栅MOSFET、环形栅MOSFET和竖直结构MOSFET。随着MOSFET向亚50nm等比例缩小,这些新结构器件将大有前途。 Compared with the traditional planar MOSFET's,MOSFET's with novel structures have better performance,such as improved SCE,ideal DIBL and sub-threshold slope,as well as higher driving ability. Five types of novel structured MOSFET's,including planar double-gate MOSFET's,FinFET's,tri-gate MOSFET's,gate-all-around MOSFET's and vertical MOSFET's,are described in the paper. As MOSFET's are scaling down to sub-50 nm,these devices are very promising.
作者 林钢 徐秋霞
出处 《微电子学》 CAS CSCD 北大核心 2003年第6期527-530,533,共5页 Microelectronics
关键词 平面双栅MOSFET FINFET 三栅MOSFET 环形栅MOSFET 竖直结构MOSFET 集成电路 MOSFET Double-gate MOSFET Fin-FET Tri-gate MOSFET Gate-all-around MOSFET Vertical MOSFET
  • 相关文献

参考文献10

  • 1[1]Philip H S, Chan W K K, Taur Y. Self-align (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel [A].. IEEE IEDM [C]. 1997.427-430.
  • 2[2]Tanaka T, Suzuki K, Horie H, et al. Ultrafast lowpower operation of p+-n+ double-gate MOSFETs[A]. IEEE Symp VLSI Tech [C]. 1994. 11-12.
  • 3[3]Suzuki K, Tanaka T, Tosaka Y, et al. Scaling theory for double-gate SOI MOSFET's [J]. IEEE Trans Elec Dev,1993; 40(12): 2326-2329.
  • 4[4]Huang X-J, Lee W-L, Kuo C,et al. Sub-50 nm Pchannel FinFET [J]. IEEE Trans Elec Dev,2001; 48(5): 880-885.
  • 5[5]Choi Y-K, King T-J, Hu C. Nanoscale CMOS spacer FinFET for the terabit era [J]. IEEE Trans Elec Dev,2002; 23 (1): 25-27.
  • 6[6]Chau R, Doyle B, Kavalieros J, et al. Advanced depleted-substrate transistors: single-gate, doublegate and tri-gate [A]. Intl Conf Sol Sta Dev Mater(SSDM)[C]. Nagoya,Japan. 2002.
  • 7[7]Colinge J P, Gao M H, Romano-Rodriguez A,et al.Silicon-on-insulator "gate-all-around device" [A].IEEE IEDM [C]. 1990. 595-598.
  • 8[8]Auth C P, Plummer J D. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's [J]. IEEE Trans Elec Dev Lett, 1997;18(2): 74-76.
  • 9[9]Risch L, Krautschneider W H, Hofmann F, et al.Vertical MOS transistors with 70 nm channel length [J]. IEEE Trans Elec Dev,1996; 43 (9):1495-1498.
  • 10[10]Yang M, Chang C-L, Carroll M, et al. 25-nm pchannel vertical MOSFET's with SiGe source-drains[J]. IEEE Trans Elec Dev Lett,1999;20 (6): 301-303.

同被引文献16

  • 1张波.功率MOSFET的研究与新发展.半导体技术,2010,35(1):1-1.
  • 2SYAU T, VENKATRAMAN P, BALIGA B J. Comparisonof ultralow specific on -resistance UMOSFET structures [J],IEEE Trans Electron Devices, 1994,41(5) :800-808.
  • 3TARUI Y, HAYASHI Y, SEKIGAWA T. Diffusion self-aligned enhance—depletion MOS-IC [ C]//Proceedings of the2nd Conference Solid State Devices. Tokyo Japan, 1970:193-198.
  • 4TSIBUKISTD,KRIEZIS E E. VVMOS power transistor: Up-per and lower bounds of the on -resistance [J]. ElectronicsLetters,1981,17( 10): 353-355.
  • 5LANE W A,SALAMA CAT, Epitaxial VVMOS power tran-sistors [J]. IEEE Tran on Electron Devices,1980,27 (2): 349-355.
  • 6TEMPLE V AK, LOVE R P,GRAY P V. A 600-volt MOS-FET designed for low on-resistance [ J]. IEEE Trans on Elec-tron Devices, 1980,27(2) :343-349.
  • 7SALAMA C A T. A new short channel MOSFET structure (U-M0SFET)[J]. Solid State Electron, 1977,20 (12):1003-1009.
  • 8LIDOW A,HERMAN T,COLLINS H W. Power MOSFETtechnology [ C]//Proceeding of International Electron DevicesMeeting. New York : Piscqtaway, 1977:79-85.
  • 9UEDA D,TAKAGI H,KANO G. A new vertical power MOS-FET structure with extremely reduced on-resistance [J].IEEETrans on Electron Devices,1985,32(1):2-6.
  • 10BALIGA B J, GIRDHAR D. Paradigm Shift in planar PowerMOSFET Technology [J]. Power Electronics TechnologyMagazine, 2003(2 ):24-32.

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部