一种适合SOC的时钟控制器IP核

An IP Core of Timer Control Unit for SOC's

随着集成电路系统的规模和复杂性的不断提高,基于IP核的SOC系统的设计已被广泛采用。与此同时,电路测试的难度不断增大,对电路的可测性设计也提出了更高的要求。文章介绍了应用于嵌入式系统的16位时钟控制器(TimerControlUnit)的IP核设计,设计中采用了JTAG可测性设计电路。

With the increasing scale and complexity of integrated circuits,the design of IP-based SOC's is now widely adopted. The test and verification of IC's become more difficult with the increasing complexity of the circuit and face new challenges. A 16-bit timer control unit is designed,which is an IP core for an embedded system. The JTAG test circuit is also adopted in the design.