基于0.18μm CMOS工艺的千兆以太网数据判决电路芯片

0. 18 μm CMOS Data Decision IC for Gigabit Ethernet

介绍了用TSMC0 18umCMOS工艺设计的千兆以太网数据判决芯片的模块及单元电路的结构,给出版图,后仿真及测试结果。该芯片采用CMOS互补逻辑的D触发器结构,功耗小于25mW,最高工作速率大于3 125Gbps,可直接用于千兆以太网物理媒介配属层的时钟数据恢复电路中。

A data decision IC based on 0.18um CMOS technology has been realized and characterized for Gigabit Ethernet. The highest operation rate of the chip is more than 3.125 Gbps with a DFF using CMOS Logic structure. The power consumption is less than 25 mW. The chip can be adopted in the clock and data recovery circuits of the physical medium attachment layer in the Gigabit Ethernet.