纠错纠删RS解码器的高速VLSI结构设计

VLSI design of high-speed architecture for Reed-Solomon decoders of correcting errors -and -erasures

在传统RS(Reed Solomon)解码器设计的基础上 ,增加一些功能模块 ,使它能够同时纠正错误和删除 .在设计过程中 ,采用比较规整的电路结构 ,实现了模块复用 ,同时降低了设计的复杂度 ;采用串行结构的多项式扩展模块 ,节省了电路面积 ,获得了运算的高速实现 .该设计应用于DVD伺服控制芯片中 ,达到了预期的性能要求 .

Based on the conventional RS(Reed-Solomon) decoder, RS decoder for correcting Errors-and-Erasures was presented by adding some modules. With the methods for modules reuse, the proposed architectures are regular and can reduce the complexity of the design. High speed and optimized area is achieved by serial architectures in the polynomials expansion module. This decoder can be used in the DVD servo control chip and meets the requirement of the expected performance.