基于SystemC的RISC CPU行为描述

Behavioral Description of RISC CPU with SystemC

探讨了一种基于SystemC的RISCCPU建模方法,建立了一个SPARC精简指令集CPU的整数单元(IU)行为级模型.该模型作为指令集仿真器(ISS),基本达到了RISCCPU的功能要求,为程序提供了一个CPU模拟平台,减少了软硬件协同设计的周期,这对片上系统SOC的实现具有重要的意义.

In this paper, a behavior model of Interger Unit(IU) which is a part of SPARC RISC is designed with SystemC. As a instruction set simulator(ISS),the CPU model achieves basic functions of RISC,and presents a simulation platform of practical CPU.At the same time,it saves the time of hardware/software codesign,which is useful for implementation of System-on-chip(SOC).