摘要
延迟线是集成电路测试系统的关键部件。本文介绍了模拟式延迟线的性能和原理 ,分析了模拟式延迟线由于干扰 ,温漂等因素的影响 ,定时分辨率很高但定时精度难以提高的情况。最后指出延迟线的集成是大势所趋 ,立足CMOS工艺的数字延迟线必将成为未来测试系统集成化的发展方向。
Delay line is a key component of IC test system. The principle and capability of analog delay line are detailed in this paper. The reason why analogdelay line has high timing resolution and common precision as a result of disturb, temperature and nonlinearity is also analyzed. Finally the direction of further research is proposed. Integration of digital delay line based on CMOS will be the trend.
出处
《现代电子技术》
2003年第24期21-23,共3页
Modern Electronics Technique
基金
北京市科技计划项目 (H0 2 0 32 0 1 4 0 330)
