嵌入式系统的适应性显式并行指令技术(英文)

Adaptive explicitly parallel instruction computing for embedded systems

利用可重构技术可以显著改善系统的性能。重点分析探讨了支持可重构技术的适应性显式并行指令技术(AEPIC)的系统模型。该系统模型由一个显式并行指令技术(EPIC)处理器和一个精细且可动态重构结构紧密连接而成,其特点在于支持动态可重构和指令合成,因此可以为不同的应用程序提供不同的动态指令集。通过AEPIC模拟器和可重构硬件Xilinx FPGA进行模拟分析以验证其有效性。实验结果表明:比起显式并行指令技术,此系统模型能够以同样的运行频率得到更高的运行速度。

Reconfigurable hardware offers the embedded systems the potential for significant performance improvements by providing support for application-specific operations. Adaptive Explicitly Parallel Instruction Computing is a prototype model such that fine-grain and dynamically reconfigurable structure is tightly coupled with a generic EPIC machine. AEPIC allows application programs to add specialized functional units yielding a dynamically varying instruction set interface to the running application without compromising current compatibility model. Two advantages of AEPIC are ① dynamic configuration support; ②application specific instruction set synthesis. In order to investigate the ideaof AEPIC's potential realistic experiments are conducted in an environment that incorporates the AEPIC simulator and actual reconfigurable hardware of Xilinx FPGA. Results show that AEPIC can achieve the similar or higher performance at a much lower execution frequency .compared with EPIC.