循环冗余校验编译码的并行处理研究及其FPGA实现

The Parallel Processing Study and FPGA Realization for CODEC of Cyclic Redundancy Check

针对高速通信信道的误码检测,在传统串行CRC的产生和校验的基础上,推导和建立了并行8位CRC的逻辑关系,并在FPGA上编程实现。同时这种并行处理方法也适合于其它位宽的CRC电路,为高速数据的可靠传输提供了可靠保障。

With the aim at error-code check of high speed communication channel, based on generation and detection of traditional serial CRC, logical circuit for 8-bit parallel CRC is deduced and set up, and the system in FPGA is realized. This parallel processing method is fit for other bit-wide CRC, and provides reliability for high-speed data transferring as well.