摘要
本文介绍一个÷5/6低功耗ECL予置分频器的设计,从降低电源电压,减小内部逻辑摆幅和寄生电容等几方面讨论了提高电路高速低功耗特性的途径。该电路采用串联电源电压结构,内部电路在-2.5V~-2.7V电源电压下工作。电路功耗仅为具有相同功能的普通ECL电路的1/6。采用3μm设计规则的氧化物隔离等平面S型双极工艺。发射极条实际尺寸2μm×9μm,晶体管f_i为3.2GHz。室温下典型功耗75mW,最高M作频率大于900MHz。
The design of a ÷5/6 low power ECL prescaler is described in the paper. Approaches to improve the high speed and low power property of the circuit are discussed in terms of the reduction of supply voltage, internal logic swing and parasitic capacitance. The structure of a serial supply voltage is adopted for the circuit and the internal circuit operates at -2. 5--2. 7V. The power consumption is only 1/6 that of a conventional ECL circuit with the same functions. A 3μm oxide isolation isoplanar S process was employed for this device. The actual size of the emitter is 2μm × 9μm and the ft, of the transistor is 3. 2GHz. The typical power consumption at room temperature is 75mW and the maxi-um operating frequency is greater than 900MHz.
出处
《微电子学》
CAS
CSCD
1992年第5期15-17,57,共4页
Microelectronics
关键词
预置分频器
频率合成器
分频器
Low power ECL prescaler, Oxide isolation isoplanar S process, Digital frequecy synthesizer