二元判定图在逻辑模拟中的应用

The Applications of Binary Decision Diagrams in Logic Simulation

逻辑模拟可分为两部分:排队和求值。后者在逻辑模拟过程中要进行成千上万次。为减少模拟时间,我们采用二元判定图描述各种集成电路的逻辑功能。由于原始二元判定图有一定的局限性,为此对它作了扩充。在此基础上建立了一个集成电路元件库,开发了相应的逻辑模拟器。该元件库内包括了Texas TTL和National CMOS手册中常用的元件。本文将讨论对二元判定图的扩充,并给出逻辑模拟器的梗概。

Logic Simulation can be divided into two procedures: queuing ICs and finding output values of them, and the latter procedure always goes through thousands of times during simulating. In order to reduce simulation time, binary decision diagrams (BDD) are used to describe logic function of a variety of ICs. Because of the limitation of original BDD, modification has been made, An IC library which consists of most common used ICs in Texas TTL and National CMOS handbook has been built up and a logic simulator based on BDD has beeen developed. The modification of BDD and the outline of the simulator will be presented in this paper.